1. Field of the Invention
The present invention relates to a power device and method of manufacturing the same and, more specifically, to a high voltage metal oxide semiconductor field effect transistor (HVMOSFET) having a Si/SiGe heterojunction structure and method of manufacturing the same, in which a breakdown voltage is held high and an on resistance is held low.
2. Discussion of Related Art
In general, power devices using a field effect include a lightly doped drain-high voltage MOSFET (LDD-HVMOSFET), a double diffused MOSFET (DMOSFET), an extended drain MOSFET (EDMOSFET), and a lateral double diffused MOSFET (LDMOSFET). These power devices are being watched with keen interest as high voltage devices because they operate at high switching speed and at a low on resistance in comparison to other power devices.
The field-effect power devices commonly include a drain that is comprised of a lightly doped region and a heavily doped region. The drain has a heterojunction structure obtained by performing an ion implantation process twice. Thus, a hot electron effect, which arises from an increase in the intensity of a vertical electric field at the end of a channel close to the drain, can be diminished. The hot electron effect leads to reductions in a small-signal output resistance and a transconductance (Gm), trapping of electrons in an oxide layer to increase a threshold voltage, and generation of a substrate current. The generated substrate current induces the operation of a parasitic bipolar transistor (BJT) between a source, a substrate, and a drain, thus a breakdown voltage VDS decreases. Accordingly, a power device should be structured such that it has a high breakdown voltage to resist to a high voltage and has a low on resistance to hold switching speed high.
FIG. 1 is a cross sectional view of a basic high voltage device, specifically, a conventional LDD-HVMOSFET.
Referring to FIG. 1, the HVMOSFET is manufactured in a semiconductor substrate 10 in which a p-well region 41 and an n-well region 51 are formed. The HVMOSFET is comprised of an N-type LDD-HVMOSFET formed in the p-well region 41 and a P-type LDD-HVMOSFET formed in the n-well region 51.
A gate oxide layer 19 is formed on the p-well region 41 over the p-type semiconductor substrate 10 on which a field oxide layer 21 is formed, and a gate electrode 20 is formed on the gate oxide layer 19. An n+ source region 16 including an n− LDD region 15 and an n+ drain region 17 are formed in the p-well region 41 on both sides of the gate electrode 20, respectively. A p+ source contact region 18 is formed on one side of the n+ source region 16, and an n-type drift region 14 is formed outside the n+ drain region 17. In the above-described N-type LDD-HVMOSFET, respective portions of the gate electrode 20, the n+ source region 16, the p+ source contact region 18, and the n+ drain region 17 are connected to metal electrodes 23 through contact holes formed in an interlayer dielectric layer 22.
Also, the gate oxide layer 19 is formed on the n-well region 51 over the p-type semiconductor substrate 10, and the gate electrode 20 is formed on the gate oxide layer 19. A p+ source region 56 including a p− LDD region 55 and a p+ drain region 57 are formed in the n-well region 51 on both sides of the gate electrode 20, respectively. An n+ source contact region 58 is formed on one side of the p+ source region 56, and a p-type drift region 54 is formed outside the p+ drain region 57. In the above-described P-type LDD-HVMOSFET, respective portions of the gate electrode 20, the p+ source region 56, the n+ source contact region 58, and the p+ drain region 57 are connected to metal electrodes 23 through contact holes formed in the interlayer dielectric layer 22.
In the N-type LDD-HVMOSFET, when a higher voltage than a threshold voltage is applied to the gate electrode 20 and a higher voltage is applied to the drain region 17 than the source region 16, a current flows from the source region 16 through a channel region disposed under the gate electrode 20 and the n-type drift region 14 into the drain region 17. In this process, the dispersion of an electric field in the lightly doped n-type drift region 14 can be obtained, thus lowering the maximum electric field intensity to ensure a high breakdown voltage. However, a low dopant concentration of the n-type drift region 14 makes it difficult to precisely control the on resistance of the channel region and precludes ensuring a low on resistance so as not to obtain a high driving current.
Since the P-type LDD-HVMOSFET operates on the same principle as the above-described N-type LDD-HVMOSFET, a detailed description thereof will be omitted here.